Senior Formal Verification Engineer

TechBiz Global

Senior Formal Verification Engineer at TechBiz Global, specializing in formal verification for Vector Unit sub-blocks. Duties include designing testbenches and verifying compliance with specifications.

Posted 7/10/2026full-timeRemote • 🇪🇸 SpainSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in formal verification methodologies, particularly in arithmetic formal verification and word-level modeling, while ensuring compliance with RISC-V Vector Extension specifications. Collaborates effectively with engineering teams to diagnose and resolve complex verification challenges.

Highest-signal resume keywords

Formal VerificationArithmetic Formal VerificationWord-Level ModelingCommercial EDA Formal ToolsHigh-Width Execution Pipelines

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Formal Testbench DesignMathematical Property WritingAlgorithmic Integrity AssuranceProof-Convergence Failure DiagnosisAlgebraic Rewriting Strategies

Soft Skills

Self-DrivenCollaborative

Tools & Technologies

Cadence JasperGold/DPVSynopsys VC FormalSiemens OneSpin

Industry Keywords

RISC-V Vector ExtensionCPU Execution PipelinesGPU Execution PipelinesDSP Execution PipelinesFloating-Point Arithmetic HardwareInteger Arithmetic Hardware

About the role

Key responsibilities & impact

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role.
Design scalable formal testbenches, write mathematical properties, and ensure the algorithmic and architectural integrity of the vector pipeline.
Work with VU microarchitects to identify deep corner-case bugs and achieve formal sign-off on complex arithmetic and execution blocks.
Design, deploy, and maintain robust formal verification environments for Vector Unit sub-blocks.
Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify floating-point and integer vector arithmetic units.
Independently diagnose and resolve proof-convergence failures using advanced reduction techniques.
Develop formal environments to mathematically prove compliance with RISC-V Vector Extension specifications.
Collaborate closely with VU simulation engineers for maximum bug-hunting efficiency.

Requirements

What you’ll need

B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team.
Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling.
Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware.
Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin).

Benefits

Comp & perks

Flexible working hours
Professional development opportunities