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Senior Formal Verification Engineer – Vector Unit
TechBiz GlobalSenior Formal Verification Engineer at TechBiz Global designing and maintaining formal verification environments. Collaborating with VU teams to ensure algorithmic integrity for vector pipelines.
Tech Stack
Tools & technologiesPython
About the role
Key responsibilities & impact- Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks
- Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies
- Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions
- Develop formal environments to mathematically prove compliance with the RISC-V Vector Extension specification
- Collaborate closely with simulation engineers to ensure maximum bug-hunting efficiency
Requirements
What you’ll need- B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science; or a Ph.D. in formal methods or computer arithmetic
- 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years)
- Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling
- Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware
- Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin)
- Native fluency in SystemVerilog and SVA; Scripting proficiency (Python, Tcl, or Bash)
Benefits
Comp & perks- Professional development opportunities
- Flexible working arrangements
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
Formal VerificationArithmetic Formal VerificationWord-Level ModelingAlgebraic RewritingHigh-Width Execution PipelinesVector Execution UnitsFloating-Point ArithmeticInteger ArithmeticScripting ProficiencyProof-Convergence Diagnosis