SiPearl

Senior Verification Engineer – Team Lead

SiPearl

full-time

Posted on:

Location Type: Hybrid

Location: Maisons-Laffitte • France

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Job Level

Senior

Tech Stack

Python

About the role

  • Define the verification platform architecture (UVM/SystemVerilog, C/C++, Python…)
  • Develop and maintain test environments, verification benches, and functional simulations
  • Plan, prioritize, and track verification activities throughout the development cycle
  • Lead and mentor a team of verification engineers
  • Collaborate with system architects, design teams, and embedded software teams.

Requirements

  • Minimum 7–10 years of experience in ASIC/SoC verification, including 3–5 years as an architect or lead
  • Proficiency in SystemVerilog/UVM, VHDL/Verilog, C/C++, Python/TCL scripting
  • Proven experience in team management and leading technical projects
  • Strong understanding of SoC architectures and communication protocols (AXI, AHB, PCIe, Ethernet…)
  • Education: Master’s degree or PhD in electronics, microelectronics, embedded computing, or equivalent
  • Languages: Fluent in French and professional working proficiency in English (reading, writing, speaking).
Benefits
  • Annual bonus*
  • Meal vouchers (60% covered by SiPearl)
  • Health insurance (70% covered by SiPearl)
  • Unlimited access and pre-paid sessions with a practitioner of your choice on our mental health partner app, moka.care
  • Technical, language, and personal development training
  • BSPCE
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
SystemVerilogUVMC++PythonTCLVHDLVerilogASIC verificationSoC verificationfunctional simulations
Soft Skills
team managementleadershipmentoringcollaborationplanningprioritizationtracking
Certifications
Master’s degreePhD