Seagate Technology

Senior Engineering Manager – HAMR Wafer Process Development

Seagate Technology

full-time

Posted on:

Location Type: Office

Location: Bloomington • Minnesota • 🇺🇸 United States

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Salary

💰 $143,395 - $209,008 per year

Job Level

Senior

About the role

  • Lead a team of highly skilled engineers and technicians responsible for the development and qualification of light-deliver (LD) and magnetic pole (MP) processes for next generation HAMR products
  • Manage a group of ICP, CMP, and optical test engineers to deliver unit process solutions for HAMR writer
  • Work with WW ICP and CMP process partner groups to define next-gen tooling to enable process roadmap
  • Define and execute optical test and tooling technology roadmap to meet the product roadmap requirement
  • Partner with other NWPD teams to implement, develop, and optimize advanced LD and MP fabrication processes, including lithography, materials, deposition, thin films, and metrology
  • Direct team resources to implement process changes, reducing wafer content and decreasing cycle time
  • Manage technology lifecycle from concept to volume launch, partnering with WW wafer production teams to transfer technologies to factory
  • Work with design team to define and execute roadmaps for device technologies and wafer process in alignment with the HDD roadmap
  • Align team objectives with organizational goals, driving schedules and deliverables
  • Oversee technology staging and intellectual property portfolio generation

Requirements

  • Bachelor's Degree in Science and Engineering-related field, such as Physics, Materials Science & Engineering, Electrical Engineering, Chemistry, Chemical Engineering, or Mechanical Engineering, and 12+ years of experience, or Master’s degree in Science and Engineering-related field and 8+ years of experience, or PHD and 5+ years of experience or equivalent education and experience
  • Expertise in wafer process development and integration for recording head fabrication
  • Hands-on experience in wafer processing, including CMP, plasma etch, and/or thin film process
  • Demonstrated success in LD and MP module development and transitioning concepts to M1 maturity
  • Strong statistical data analysis skills and a solid understanding of DOE for wafer process development
  • Leadership experience either in project management or team lead roles
Benefits
  • Eligibility to participate in discretionary bonus program
  • Medical, dental, vision, and life insurance
  • Short-and long-term disability
  • 401(k)
  • Employee stock purchase plan
  • Health savings account
  • Dependent care and healthcare spending accounts
  • Paid time off, including 12 holidays
  • Flexible time off
  • Minimum of 48 hours of paid sick leave
  • 16 weeks of paid parental leave

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard skills
wafer process developmentCMPplasma etchthin film processstatistical data analysisdesign of experiments (DOE)optical testlithographymaterials depositionmetrology
Soft skills
leadershipproject managementteam managementorganizational alignmentschedule managementdeliverable tracking
Certifications
Bachelor's DegreeMaster's DegreePhD