Micro-architect/Logic Designer, Coherent Interconnect

Samsung Electronics

Micro-Architect/Logic Designer leading the development of coherent interconnect IP at Samsung. Collaborating with architects and other teams for high-performance computing devices.

Posted 6/12/2026full-timeSan Jose • California, Texas • 🇺🇸 United StatesSeniorLead💰 $151,000 - $251,800 per yearWebsite

About the role

Key responsibilities & impact

Responsible for leading the micro-architecture development of custom coherent interconnect IP and last level cache blocks
Interacting with system architects, verification, performance/power, and design implementation teams
Owning and driving the critical coherent interconnect related RTL design, performance and power optimization
Work on logic debug and timing closure of the design
Drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks
Partner with architects to help define next-generation Samsung coherent interconnects and LLC
Perform microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
Work alongside the verification team to verify the functionality and correctness of the design
Collaborate with implementation to achieve timing and area
Produce quality RTL on schedule meeting PPA goals
Engage with performance and power team on achieving performance and power goals
Work with the physical design and CAD team to resolve implementation level details
Help mentor junior engineers in the team

Requirements

What you’ll need

10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
Demonstrated successful architectural through RTL design experience on high performance digital designs
Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
Knowledge of system caches and directory snoop filter protocols
Familiarity with different on-chip network topologies: mesh, ring, crossbar
Experience in leading and mentoring a team of engineers
Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
Knowledge of memory subsystem design including coherent cache design
Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team

Benefits

Comp & perks

medical
dental
vision
life insurance
401(k)
free onsite lunch
employee purchase program
tuition assistance (after 6 months)
paid time off
student loan program
wellness incentives
MBO bonus compensation
long term incentive plan
relocation

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Hard Skills & Tools

RTL designVerilogASIC design flowtiming analysislogic synthesisDFTfloor-planningECOlab debugmicroarchitecture development

Soft Skills

leadershipmentoringcommunicationinterpersonal skillscollaboration

Certifications

Bachelor’s degree in Computer ScienceBachelor’s degree in Computer EngineeringMaster’s degreePhD