Apply

Ready to go for it?

AI Apply speeds things up—apply directly if you prefer.

FREE ACCESS
5,000–10,000 jobs/day
JobTailor Logo

See all jobs on JobTailor

Search thousands of fresh jobs every day.

Discover
  • Fresh listings
  • Fast filters
  • No subscription required
Create a free account and start exploring right away.
Samsung Electronics

SoC Architect, Memory Subsystem

Samsung Electronics

. As a SoC Architect, define and drive the development of innovative SoC memory and cache subsystems .

Posted 5/16/2026full-timeSan Jose • California, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $151,000 - $251,800 per yearWebsite

Tech Stack

Tools & technologies
Android

About the role

Key responsibilities & impact
  • As a SoC Architect, define and drive the development of innovative SoC memory and cache subsystems
  • Identify, propose, and deliver new SoC memory architectures and features for premium mobile and related product platforms
  • Contribute to high-impact deliverables, with the freedom to experiment and explore novel ideas to challenge existing norms
  • Create detailed designs and specifications for memory subsystems, including memory interfaces, controllers, and caches
  • Analyze PPA trade-offs and optimize memory subsystem performance, power consumption, and area utilization
  • Work closely with software, hardware, and validation teams to ensure memory subsystem designs meet system requirements
  • Create and maintain detailed documentation of memory subsystem designs, including architecture, implementation, and verification plans
  • Stay up-to-date with emerging memory technologies and recommend their adoption in SoC designs

Requirements

What you’ll need
  • 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a PhD
  • Experience designing and developing complex digital systems and SoC memory architectures
  • Strong understanding of memory hierarchies, memory interfaces (e.g., DDR, LPDDR, HBM), and memory controllers is crucial
  • Detailed knowledge of cache subsystems including caching policies and understanding the tradeoffs of latency, bandwidth and hierarchies
  • Knowledge of memory scheduling, bandwidth management, and latency optimization
  • High familiarity with existing and emerging JEDEC memory standards
  • Experience with cache coherence protocols and bus protocols (e.g., CHI, ACE, AXI) is a plus
  • Experience with the Android ecosystem and analysis tools is a plus
  • Experience with Arm architecture and ecosystem is a plus

Benefits

Comp & perks
  • medical
  • dental
  • vision
  • life insurance
  • 401(k)
  • free onsite lunch
  • employee purchase program
  • tuition assistance (after 6 months)
  • paid time off
  • student loan program
  • wellness incentives

ATS Keywords

✓ Tailor your resume
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
SoC architecturememory subsystemsmemory interfacesmemory controllersPPA analysislatency optimizationcache subsystemsmemory schedulingbandwidth managementcache coherence protocols
Soft Skills
innovationcollaborationdocumentationproblem-solvingcommunication