Own or contribute to the successful completion of FPGA-based designs
Verify designs utilizing self-checking techniques
Create complete documentation including verification plan and report
Demonstrate self-motivation, with little supervision required
Work cooperatively with systems, hardware, software engineers, and program management
Support internal and external technical reviews

Requirements

Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM)
Minimum of 5 years of prior relevant experience
Digital design verification
Proficient in SystemVerilog for verification
Hands-on experience verifying designs using UVM-based testbenches
Proficiency with industry-standard simulators (e.g., Questa, VCS, Xcelium)
Experience designing FPGAs using VHDL/Verilog
Solid understanding of constrained-random verification
Familiarity with AXI, PCIe, Ethernet, DDR protocols
Ability to develop and maintain verification plans
Experience with version control systems (e.g., Git, ClearCase, SVN)
Experience with UVMF (UVM Framework)
Familiarity with Vivado and Quartus FPGA simulation flows
Experience with scripting languages (Python, Tcl, Perl)
Familiarity with SLURM workload manager
Prior experience mentoring junior verification engineers
Existing DoD security clearance

Benefits

medical
dental
vision
life insurance
short-term disability
long-term disability
401(k) match
flexible spending accounts
flexible work schedules
employee assistance program
Employee Scholar Program
parental leave
paid time off
holidays

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

FPGA designdigital design verificationSystemVerilogUVM-based testbenchesVHDLVerilogconstrained-random verificationscripting languagesversion control systemsUVMF

Soft Skills

self-motivationcooperationmentoring

Certifications

DoD security clearance