Identify requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
Recommend new tools and practices for continuous improvement in the group’s ASIC / FPGA design flow
Contribute to engineering estimates for new program pursuits
Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status

Requirements

Experience in RTL coding and simulation in Verilog or VHDL
Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure
Experience in Testbench development for the verification of RTL blocks using System Verilog
Proficient using ASIC and/or FPGA simulation and synthesis tools (e.g., ModelSim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
Familiarity with revision control concepts and tools (e.g., Git, Subversion)
Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience

Benefits

Medical, dental, and vision insurance
Three weeks of vacation for newly hired employees
Generous 401(k) plan that includes employer matching funds and separate employer retirement contribution, including a Lifetime Income Strategy option
Tuition reimbursement program
Student Loan Repayment Program
Life insurance and disability coverage
Optional coverages you can buy pet insurance, home and auto insurance, additional life and accident insurance, critical illness insurance, group legal, ID theft protection
Birth, adoption, parental leave benefits
Ovia Health, fertility, and family planning
Adoption Assistance
Autism Benefit
Employee Assistance Plan, including up to 10 free counseling sessions
Healthy You Incentives, wellness rewards program
Doctor on Demand, virtual doctor visits
Bright Horizons, child and elder care services
Teladoc Medical Experts, second opinion program
And more!

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

RTL codingVerilogVHDLdigital circuit architecturetiming analysistiming closureTestbench developmentSystem VerilogASIC designFPGA design

Soft Skills

technical leadershipplanning activitiesreporting status