Advanced Layout Automation Engineer

Quantinuum

Advanced Layout Automation Engineer working with Ion Trap fabrication team at Quantinuum. Leveraging layout automation tools and machine learning to accelerate chip design processes.

Posted 5/14/2026full-timeBrooklyn Park • Minnesota • 🇺🇸 United StatesMid-LevelSenior💰 $116,000 - $140,000 per yearWebsite

Tech Stack

Tools & technologies

LinuxPython

About the role

Key responsibilities & impact

Work closely with a team of design and fabrication scientists to lay out masks for next generation ion traps
Develop and demonstrate scripting and automation capabilities/tools for routing as well as verification in advance of their need that will accelerate our layout timeline
Collaborate with a cross-functional team to ensure designs are consistent with good layout practices
Work with our foundries to ensure design and tapeout is consistent with their PDKs and/or best practices

Requirements

What you’ll need

Bachelor’s degree minimum
Minimum 3+ years' experience in hierarchical IC or MEMS layout using EDA tools such as Cadence Virtuoso, klayout from initial conception through tapeout
Due to Contractual requirements, must be a U.S. Person defined as, U.S. citizen permanent resident or green card holder, workers granted asylum or refugee status.
Due to national security requirements imposed by the U.S. Government, candidates for this position must not be a People's Republic of China national or Russian national unless the candidate is also a U.S. citizen.
Bachelor’s degree in electrical engineering, Mechanical Engineering, Computer Science, Physics or a related field preferred
Minimum 5 years’ experience with integrated circuit layout and simulation in Cadence Virtuoso, including novel development and leverage of automation tools, use of space-based routers, concurrent layout and ML/AI tools
Demonstrated use of automation, scripting and/or machine learning to accelerate workflows and time to tapeout
Minimum 5 years’ experience taping out layouts and delivering to mask shops
Experience laying out masks for external (i.e., non-captive) foundries and working with multiple PDKs as well as incorporating new design rules
Experience using Linux OS
Familiarity with SKILL language script and Python for layout (GDSpy, etc.)
Minimum 2 years’ experience with MEMS layout tools such as L-Edit, K-Layout or similar
Experience with silicon photonics layout.
Experience working in a cross-functional, R&D team environment

Benefits

Comp & perks

A competitive salary and innovative, game-changing work
Flexible work schedule
Employer subsidized health, dental, and vision insurance
401(k) match for student loan repayment benefit
Equity, 401k retirement savings plan + 12 Paid holidays and generous vacation + sick time
Paid parental leave
Employee discounts

ATS Keywords

✓ Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

IC layoutMEMS layoutscriptingautomationmachine learningtapeoutsilicon photonics layoutdesign ruleshierarchical layoutverification

Soft Skills

collaborationcommunicationteamworkproblem-solvingorganizational skills

Certifications

Bachelor's degreeBachelor's degree in electrical engineeringBachelor's degree in Mechanical EngineeringBachelor's degree in Computer ScienceBachelor's degree in Physics