Senior Product Manager, Hardware – NPU IP

quadric.io

Senior Product Manager at Quadric managing GPNPU hardware roadmap. Executing customer needs for neural processing units at the architectural level with a focus on integration and safety.

Posted 7/8/2026full-timeBurlingame • California • 🇺🇸 United StatesSenior💰 $200,000 - $250,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in hardware product management, including customer engagement, architecture decision-making, and competitive intelligence analysis. Proficient in integrating customer feedback into product roadmaps and managing complex silicon product lifecycles.

Highest-signal resume keywords

Hardware Product ManagementCustomer EngagementArchitecture Decision-MakingNPU/AI Accelerator ArchitectureSoC Integration

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

Silicon Product ManagementArchitecture ReviewsFunctional Safety PositioningFMEDA WorkSoC IntegrationDSP/Vector ComputeSemiconductor IP LicensingAPI WrappersCustom RTL HooksPerformance Counters

Soft Skills

Customer First MindsetTechnical CommunicationCollaboration with ArchitectsProblem SolvingStakeholder Engagement

Tools & Technologies

Agentic AI ToolsClaude CodeCursorAXI4ACE-Lite

Industry Keywords

Tier 1 AutomotiveOEM SoC TeamsHardware RoadmapCompetitive IntelligenceIntegration Guide

About the role

Key responsibilities & impact

Hardware roadmap. Translate customer requirements, competitive pressure, and architectural constraints into a track-by-track feature list with explicit gating — what ships, what slips, what gets cut.
Architecture freeze. Build the case for contested architecture decisions (e.g., dedicated requant unit vs. wider MAC array), run the tradeoff with the architects, and bring a recommendation to the PSC.
Customer engagement. Named hardware product owner for anchor accounts. Present new features, ingest formal architecture feedback, and convert it into roadmap input.
IP usability. Find what customers are silently working around — API wrappers, glue logic, custom RTL hooks, workaround scripts.
Hardware competitive intelligence. Track Synopsys NPX6, Arm Ethos-U85, Ceva NeuPro-M, VeriSilicon Vivante, and NVIDIA Jetson at the architectural level. Translate competitor moves into specific feature requirements before gaps appear in customer evals.
SoC integration positioning. Decide which integration knobs (AXI4/ACE-Lite, CoreSight, power-domain partitioning, performance counters) are exposed, which are productized, and how they're described in the integration guide.
Functional safety positioning. Sequence FMEDA work, lockstep configurations, and safety-island architecture.

Requirements

What you’ll need

5–8 years of PM experience on hardware or silicon products. Senior IC background.
Customer-facing track record - You have run architecture reviews with sophisticated technical buyers — Tier 1 automotive, OEM SoC teams
IP-licensing rhythm - Customers integrate our IP for 18–24 months before silicon ships. Decisions today appear in production volume in 2028.
Agent-pilled - You use agentic AI tools daily (Claude Code, Cursor, or equivalent) to produce work.
Customer first
Direct experience with at least two of: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, semiconductor IP licensing
EE/CE/CS engineering degree or equivalent depth
Experience with in-person technical customer reviews
Bay Area resident or willing to relocate to Burlingame

Benefits

Comp & perks

Competitive salary and meaningful equity
Medical, dental, and vision plan options starting on day one
401(k) retirement plan
Flexible paid time off (unlimited, non-accrual)
Company-provided lunches and a stocked kitchen
Monthly parking or Caltrain pass
Downtown Burlingame office, walking distance from Caltrain