Staff Physical Design Engineer

Powerlattice Inc

Staff Physical Design Engineer at PowerLattice implementing advanced SoC designs. Collaborating on floorplanning, routing, and physical verification for next-gen chiplet solutions.

Posted 4/12/2026full-timeChandler • Arizona, Texas • 🇺🇸 United StatesLeadWebsite

About the role

Key responsibilities & impact

Drive the implementation of complex SoC designs from netlist to tapeout.
Develop and own chip-level and block-level floorplans, including macro placement and partitioning.
Define and implement power distribution networks, including digital power grid creation.
Integrate and ensure robust power connectivity for analog blocks and ESD structures.
Optimize floorplan for performance, congestion, and power integrity.
Perform and manage special routing for sensitive analog signals, ensuring signal integrity and isolation.
Collaborate closely with analog designers on layout constraints, shielding, and noise mitigation.
Ensure proper integration of analog macros within digital environments.
Execute standard cell placement, optimization, and congestion management.
Perform clock tree synthesis (CTS) and clock optimization.
Drive global and detailed routing with focus on timing, SI, and manufacturability.
Implement timing and functional ECOs to achieve design closure.
Run and analyze physical verification flows including DRC, LVS, and antenna checks.
Debug and resolve all layout violations to achieve clean signoff.
Drive timing closure across all corners and modes.
Collaborate with STA teams on setup/hold closure and constraint validation.
Optimize design for PPA (power, performance, area) targets.

Requirements

What you’ll need

8+ years of experience in physical design for advanced SoCs
Strong hands-on expertise in:
Floorplanning and power planning (including analog/ESD integration)
Place-and-route flows (placement, CTS, routing, ECOs)
Physical verification (DRC, LVS, antenna) and signoff closure
Solid understanding of:
Timing analysis and closure techniques
Signal integrity, IR drop, and electromigration considerations
Advanced technology nodes and design rules
Experience with industry-standard EDA tools (e.g., Cadence Innovus, Synopsys ICC2, Calibre)
Strong problem-solving skills and ability to debug complex layout issues.
Experience with mixed-signal SoCs and analog/digital co-design (preferred)
Experience with power integrity analysis tools (preferred)
Track record of successful tapeouts in advanced nodes (preferred)

Benefits

Comp & perks

Competitive salary
Stock options
Comprehensive benefits package including health, dental, vision, and 401(k)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

SoC designfloorplanningpower planningplace-and-routephysical verificationtiming analysissignal integritypower integrityclock tree synthesisrouting

Soft Skills

problem-solvingcollaborationdebugging