Verify FPGA-based designs critical to Planet’s satellite imaging operations
Create and improve verification environments using SystemVerilog and formal tools
Collaborate with RTL, software, electrical, RF, camera, and firmware engineers to develop verification plans and deliver validated designs
Write and debug tests to deliver functionally correct blocks and systems
Improve coverage and streamline hardware integration testing
Automate verification flows and work with AI&T to develop production testing flows
Contribute to development of FPGA infrastructure and integration of commercial IP blocks
Assist in lab-based debugging and hardware bring-up for satellite systems
Requirements
Bachelor’s degree in Electrical Engineering, Computer Science or similar
6+ years of experience developing DV test plans, verifying RTL using SystemVerilog, and assisting in lab-based debugging of FPGA-based digital designs with processors
Expertise in scripting and programming (Python, C++, shell)
Proficiency of version control systems (eg., git) and managing releases to production