Omni Design Technologies, Inc.

Communications

• Define system architecture for next-generation multi-antenna and SDR-based communication platforms, influencing product strategy and long-term roadmap planning.
• Lead technical engagement with strategic customers, representing system trade-offs, negotiating performance specifications, and aligning joint integration plans.
• Architect and maintain MATLAB and analytical models capturing the full signal chain, including channel modeling, quantization noise allocation, SNR budgeting, interplay of RF non-linearities, and DSP algorithm design constraints.
• Generate precise block-level specifications for digital baseband, calibration engines, channel processing, mixed-signal converters, and RF interfacing elements; ensure internal teams understand the architectural rationale behind these specifications.
• Drive alignment between digital architecture, signal processing algorithms, mixed-signal circuit selections, ADC/DAC dynamic range decisions, LO/subsystem noise considerations, and thermal/power constraints.
• Collaborate with validation and silicon bring-up teams to ensure post-silicon results trace back to modeled assumptions; define measurement-level KPIs and debug methodologies when deviations arise.
• Provide architectural guidance to system engineers, signal processing developers, and hardware design teams; develop reusable models, internal best practices, and system-level methodologies.
• Participate in internal architecture reviews, contribute to core IP innovation strategy, and represent the company in technical engagements, standards-relevant discussions, and key customer milestones.

Principal – Lead Wireless Communications System Architect

Engineer

• The senior analog & mixed-signal layout designer will be responsible for the layout of cutting edge, high performance, high speed CMOS data converters in foundry CMOS process nodes in 2nm, 3nm, 5nm, 6nm, 7nm, 16nm, and 28nm.

Lead Analog & Mixed-Signal Layout Engineer

Architect

• SerDes architect and development lead focused on PAM4 ADC and DAC based wireline technologies
• The successful candidate in this role will work with customers to understand requirements
• Will lead the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market

Senior SerDes Architect – Lead

Designer

• Develop cutting-edge circuits and architectures for ultra-high speed wireline communication systems
• Drive the development of high performance transistor level design starting from initial specification
• Supervise design and layout
• Perform silicon evaluation and characterization
• Introduce the final product to market

Principal – Lead Wireless Communications System Architect

Lead Analog & Mixed-Signal Layout Engineer

Senior SerDes Architect – Lead

Senior SerDes Analog Design