Sustaining Electrical Engineer
Littelfuse
Python
Senior High-Performance ASIC Timing Engineer
NVIDIA
full-time
Posted on:
Origin: • 🇺🇸 United States • California
Visit company websiteSalary
💰 $136,000 - $264,500 per year
Job Level
Senior
Tech Stack
PerlPython
About the role
- Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, GPU and SOC designs
- Own static timing analysis and convergence of high-performance designs
- Set up timing constraints, perform timing analysis and closure, and implement ECOs
- Define and maintain timing methodologies and flows
- Find tradeoffs and balance between power, area, congestion, and timing
- Collaborate with cross-functional teams and physical design groups to achieve timing closure
Requirements
- BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience in ASIC Design and Timing
- Hands-on experience in STA tools, ECO implementation, and timing closure of high-speed designs
- Strong background and experience in timing constraints generation, clocking, process variations and signal integrity
- Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies
- Familiarity with methodology and tools, logic synthesis, equivalence checking
- Strong interpersonal and communication skills and ability to collaborate with cross-functional teams
- Strong understanding of timing and physical design fundamentals
- (Preferred) Familiarity with high performance mixed-signal designs, and SPICE simulation
- (Preferred) Deep understanding of complex designs and the ability to plan and craft timing critical paths
- (Preferred) Background and expertise in high frequency design closure at subsystem level
- (Preferred) Ability to develop new methodologies/flows as well as workflows to aid timing convergence
