Senior Physical Verification Engineer, VLSI Implementation
NVIDIA
full-time
Posted on:
Location Type: Office
Location: Santa Clara • California • Texas • United States
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Salary
💰 $136,000 - $264,500 per year
Job Level
About the role
- Responsible for support and debug of physical implementation GPU and SOC reticle-sized chips, coordinating with the PNR team to achieve SOL tape-out – including feedback recognition and correlation.
- Determining physical verification methodologies to improve workflow efficiency and timely issue detection.
- Integrate new workflows and checks into larger workflow automation systems.
- Participate in developing physical verification flows for new technologies - DRC, LVS, Antenna flows - improving automation and expert workflows.
- TSMC A16 rules and tape-out experience is preferred.
Requirements
- BS/MS in Electrical Engineering or related field (or equivalent experience)
- Minimum 4+ years of physical implementation experience with physical verification build and debug.
- Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
- Strong knowledge and experience with Physical Verification debug of shorts/compare results across DRC/LVS/Antenna related issues.
- Direct experience with ICV and Calibre runsets for physical verification of DRC/LVS/Antenna.
Benefits
- equity
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Applicant Tracking System Keywords
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Hard Skills & Tools
physical implementationphysical verificationdebugDRCLVSAntenna flowsworkflow automationchip designFloor planningPlace and Route
Soft Skills
coordinationworkflow efficiencyissue detection
Certifications
BS in Electrical EngineeringMS in Electrical Engineering