Investigate opportunities to improve communication performance by identifying bottlenecks in today's systems
Design and implement new communication technologies to accelerate AI and HPC workloads
Explore innovative solutions in HW and SW for our next generation platforms as part of co-design efforts involving GPU, Networking, and SW architects
Build proofs-of-concept, conduct experiments, and perform quantitive modeling to evaluate and drive new innovations
Use simulation to explore performance of large GPU clusters (think scales of 100s of 1000s of GPUs)

Requirements

M.S./Ph.D. degree in CS/CE or equivalent experience
5+ years of relevant experience
Excellent C/C++ programming and debugging skills
Experience with parallel programming models (MPI, SHMEM) and at least one communication runtime (MPI, NCCL, NVSHMEM, OpenSHMEM, UCX, UCC)
Deep understanding of operating systems, computer and system architecture
Solid in fundamentals of network architecture, topology, algorithms, and communication scaling relevant to AI and HPC workloads
Strong experience with Linux
Ability and flexibility to work and communicate effectively in a multi-national, multi-time-zone corporate environment

Benefits

equity
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Applicant Tracking System Keywords

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Hard Skills & Tools

CC++parallel programmingMPISHMEMNCCLNVSHMEMOpenSHMEMUCXUCC

Soft Skills

communicationflexibilitycollaboration

Certifications

M.S. degreePh.D. degree