Lead all block/chip level physical design (PD) activities including floor plans, abstract view generation, RC extraction, PNR, STA, EM, IR drop, DRCs and schematic-to-layout verification.
Work in collaboration with design team to address design challenges and achieve timing/physical closure.
Help team members in debugging tool/design related issues and provide proactive intervention for difficult design problems.
Constantly look for improvements in the RTL2GDS flow to improve PPA (power, performance, area).
Responsible for all aspects of physical design and implementation of GPUs and other ASICs targeted at desktop, laptop, workstation, and mobile markets.
Requirements
BE/BTECH/MTECH, or equivalent experience.
1+ years of experience in Physical Design.
Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies.
Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
Expertise on high frequency design methodologies.
Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification.
Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred.
Well versed with timing constraints, STA and timing closure.
Good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
Proficiency using Perl, Tcl, Make scripting is preferred.
Ability to multi-task and flexibility to work in global environment.