Improve and validate flows for Prime-Time, Prime-Shield and Tempus STA QOR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation.
Develop custom flows for validating QOR of ETM models, both of std cells and custom IPs.
Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging, self-heating, thermal impact, IR drop etc.
Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.
Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.
Work on various aspects of STA flow, constraints, timing, and power optimization.

Requirements

MS or PhD in Electrical or Computer Engineering (or equivalent experience)
5 years of industry experience in developing and supporting STA flow
Good problem-solving skills
Excellent programming skills in Python, TCL, PERL
Disciplined coder who understands the importance of having automated regression tests
Solid knowledge in CMOS design, clocking, and timing of synchronous circuits
Good understanding of mathematics/physics fundamentals of circuit design.

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

PythonTCLPERLSTA flow developmentautomated regression testsCMOS designtiming optimizationpower optimizationQOR metricsdeep submicron physical effects

Soft Skills

problem-solvingcollaborationdiscipline

Certifications

MS in Electrical EngineeringPhD in Electrical EngineeringMS in Computer EngineeringPhD in Computer Engineering