Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC at the block/partition level and top level
Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation
Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout
Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency

Requirements

B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred)
5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes
Proven track record of driving designs through the complete RTL-to-GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification
Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi-voltage domain architectures
Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and sign-off timing analysis (MCMM STA) using complex constraints
Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle
Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure
Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations
Expert-level command of industry-standard tool suites for end-to-end physical design flows
Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations for enhanced design efficiency
Specialized experience in the physical design of blocks and partitions containing high-speed SerDes IPs, such as PCIe, CXL, C2C, and Die-to-Die interfaces a plus

Benefits

equity
health insurance

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

synthesisfloorplanningplace & routetiming constraintsUPFLECPPA optimizationRTL-to-GDSII flowclock tree synthesispower grid design

Soft Skills

leadershipcollaborationproblem-solvingcommunicationorganizational skills

Certifications

B.S. in Electrical EngineeringB.S. in Computer EngineeringM.S. in Electrical EngineeringM.S. in Computer EngineeringPh.D. in Electrical EngineeringPh.D. in Computer Engineering