NVIDIA

Senior Software R&D Engineer, Digital Logic Synthesis

NVIDIA

full-time

Posted on:

Location Type: Hybrid

Location: Santa Clara • California • Texas • United States

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Salary

💰 $168,000 - $264,500 per year

Job Level

Senior

About the role

  • Invent and develop new algorithms for RTL synthesis, digital logic optimization, graph-based RTL traversal, analysis, and manipulation.
  • Build physical-aware synthesis techniques using placement/congestion/timing feedback to improve PPA.
  • Develop strategies for rapidly analyzing the RTL change impact on timing, power, area, and impact to DFT, clocking, and power delivery on design.
  • Prototype and evaluate ML methods (e.g., GNNs, RL, models) to guide optimization decisions; integrate successful approaches into production.
  • Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.
  • Collaborate with design teams to facilitate deployment of solutions and actively drive the roadmap of increasing hardware design productivity.

Requirements

  • MS or PhD in Electrical Engineering or Computer Science or equivalent experience
  • 6+ years experience in EDA software and/or VLSI flows, with significant work in logic synthesis or digital optimization.
  • Strong CS fundamentals and modern C++ experience (templates/STL, concurrency libraries, profiling and performance optimization, data structures, algorithms, performance, concurrency, testing).
  • Solid understanding of RTL (Verilog/SystemVerilog) and digital design concepts (timing, clocking, DFT basics, power intent).
  • Expertise in EDA techniques, including logic synthesis, global route, static timing analysis, power & area optimization and SAT solvers
  • Good communication and interpersonal skills.
Benefits
  • equity
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Applicant Tracking System Keywords

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Hard Skills & Tools
RTL synthesisdigital logic optimizationgraph-based RTL traversalphysical-aware synthesisC++VerilogSystemVerilogEDA techniquesstatic timing analysispower optimization
Soft Skills
communication skillsinterpersonal skills
Certifications
MS in Electrical EngineeringPhD in Computer Science