Improving Voltage/Frequency/Power/Thermal Envelope of Nvidia Products
Architect new Chip/System features to improve testable power, V/F, speed grades, temp, or test time
Define the methodology for how manufacturing tests, SRAM, binning, or package technology constraints should be incorporated into product V/F curves, vmin, and TGP.

Requirements

Master’s degree (MS) or equivalent experience in Electrical Engineering (EE), Computer Engineering (CE), Computer Science (CS), Systems Engineering, or related field
8+ years of experience
Deep knowledge of System and chip circuits to improve DVFS, Binning, or Power/thermal management features for advanced SOCs/GPUs
Comfortable in both the Pre-Silicon test strategy and hands-on lab prototyping of system features
Python/Perl Scripting

Benefits

Competitive salaries
Benefits package
Equity

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

Voltage/Frequency/Power managementThermal Envelope optimizationChip/System architectureManufacturing test methodologySRAM technologyBinning techniquesPower/thermal managementPre-Silicon test strategyLab prototypingPython scripting

Certifications

Master’s degree in Electrical EngineeringMaster’s degree in Computer EngineeringMaster’s degree in Computer ScienceMaster’s degree in Systems Engineering