Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
Participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
Craft designs for static timing analysis, power and noise analysis and back-end verification.

Requirements

BSEE (MSEE preferred) or equivalent experience.
5 years of experience in large VLSI physical design implementation on 5nm, 4nm and 3nm technology.
Your successful track record of delivering designs to production is a requirement.
Shown experience in Power, Performance and Area improvement Initiatives is a plus.
Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, SeaHawk) and Mentor Graphics.
Deep understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers, PLLs.
Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/route and tapeout solutions.
Strong analytical and debugging skills required.
Proficiency using Python, Perl, Tcl, Make scripting is helpful.

Benefits

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Applicant Tracking System Keywords

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Hard Skills & Tools

VLSI physical designstatic timing analysispower analysisnoise analysisback-end verificationtiming closureplace/routeRC extractiondebuggingscripting

Soft Skills

analytical skills

Certifications

BSEEMSEE