NVIDIA

Senior ASIC Timing Engineer

NVIDIA

full-time

Posted on:

Location Type: Office

Location: Santa ClaraCaliforniaNorth CarolinaUnited States

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Salary

💰 $136,000 - $218,500 per year

Job Level

About the role

  • Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for Nvidia’s GPUs, CPUs, DPUs, and SoCs at block level, cluster level, and full chip level.
  • Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
  • Contribute to Cutting-Edge Projects: Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.

Requirements

  • BS (or equivalent experience) in Electrical or Computer Engineering with 5 years experience or MS (or equivalent experience) with 2 years’ experience in Timing and STA
  • Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
  • Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
  • Expertise in physical design and optimization e.g., placement, routing, logic restructuring, etc. to improve timing and power.
  • Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
  • Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.
Benefits
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Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools
Static Timing Analysistiming convergencetiming constraints generationtiming path analysisECOscrosstalk analysisnoise analysisphysical designplacementrouting
Soft Skills
collaborationleadership