Drive physical design integration and implementation of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level
Drive RTL integration, synthesis, along with all physical netlist deliverables across various milestones
Drive formal equivalence checking, netlist quality checks, asynchronous checking including clock domain crossing checks and MTBF analysis, etc.

Requirements

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 3+ years’ experience in RTL integration and netlisting domains.
Strong understanding of RTL and RTL hierarchy and associated infrastructures
Hands on experience with logic synthesis and associated verification such as equivalence checking
Background in gate level netlist verification and completeness with respect to power, testability, etc
Expertise and in-depth knowledge of industry standard EDA tools.
Expertise in understanding on clock-domains, async interfaces and MTBF analysis
Solid understanding of Physical Design flows, design constraints, timing and power convergence
Proficiency in programming/scripting languages (Python, TCL etc) and/or AI tools (Cursor, Copilot, etc).

Benefits

Eligible for equity and benefits.

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

RTL integrationnetlistinglogic synthesisequivalence checkinggate level netlist verificationphysical design flowstiming convergencepower convergenceprogramming languagesscripting languages