ASIC Clocks Design Engineer
NVIDIA
full-time
Posted on:
Location Type: Hybrid
Location: Santa Clara • California • Texas • United States
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Salary
💰 $100,000 - $166,750 per year
Tech Stack
About the role
- Architecting the clock domain to satisfy functional, physical and testing design requirements
- Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints
- Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL
- Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking
- Deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams
- Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup
Requirements
- BS or higher in Electrical Engineering (or equivalent experience)
- Understanding of logic optimization techniques and PPA trade-offs
- Excellent interpersonal skills and ability to collaborate with multiple teams
- Experience in RTL design (Verilog), verification and logic synthesis
- Strong coding skills in python or other industry-standard scripting languages
Benefits
- equity
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Applicant Tracking System Keywords
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Hard Skills & Tools
RTL designVeriloglogic synthesispower optimizationtiming closureDFxphysical implementationclocking topologiesPPA trade-offsscripting languages
Soft Skills
interpersonal skillscollaborationteamwork
Certifications
BS in Electrical Engineering