RTL Design Engineer
Niobium Microsystems
full-time
Posted on:
Location Type: Remote
Location: Remote • Ohio • 🇺🇸 United States
Visit company websiteJob Level
Mid-LevelSenior
Tech Stack
PerlPython
About the role
- Participate in architectural feasibility studies
- Develop micro-architecture specifications based on the SoC requirements
- Design, implement and integrate complex SoC blocks
- Develop block-level test cases to deliver fully functional designs
- Develop synthesis constraints and resolve timing issues
- Resolve Lint, CDC, and DFT related issues
- Identify and resolve RTL and GLS failures at block and chip level
- Participate in ECO implementation
- Assist with silicon bring-up
Requirements
- 5 or more years of relevant industry experience
- Involvement in product designs in a production setting
- RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
- Third Party IP Integration experience
- Logic synthesis and static timing analysis
- SoC design flow including chip-level design, block/IP design and behavioral modeling
- Modeling SoC architectures with FPGAs
- Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
- Experience with RISC-V architecture
- Working knowledge of PCIe and DDR
- Clock domain crossing methodologies
- Scripting languages such as Python, Perl, Tcl, shell, etc.
- Strong familiarity with EDA tools
- Strong problem-solving and debugging capabilities
- Working knowledge of SoC design with CHISEL (desired but not required)
- Asynchronous logic design (desired but not required)
Benefits
- Competitive salaries
- Employer paid health care
- Employer contribution to health savings account
- Flexible time off
- Flexible work location with remote options
- 401K employer match
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
RTL DesignSystemVerilogVerilogLogic synthesisStatic timing analysisSoC design flowFPGAsRISC-V architecturePCIeDDR
Soft skills
problem-solvingdebugging