ASIC Physical Design Lead
Niobium Microsystems
full-time
Posted on:
Location Type: Remote
Location: Remote • 🇺🇸 United States
Visit company websiteJob Level
Senior
About the role
- End-to-End Physical Implementation Leadership
- Own and lead all physical design activities from RTL handoff, floorplanning, and PnR through final GDSII delivery.
- Define execution strategy, schedules, design methodology, and quality checkpoints for the entire physical design flow.
- Floorplanning & SoC Integration
- Architect and execute floorplanning strategies for large, hierarchical SoCs, including: IP integration and macro placement
- Physical partitioning and hierarchy definition
- Power grid architecture and clock distribution topology
- DIE size, aspect ratio, and physical constraints
- Collaborate with Architecture and RTL teams to ensure physical feasibility, timing closure readiness, and area/power targets.
- Place & Route + Timing Closure
- Lead block-level and top-level PnR using industry standard EDA tools (Cadence, Synopsys).
- Drive timing convergence across corners, modes, voltage domains, and operating conditions.
- Own optimization for PPA (Power, Performance, Area), congestion mitigation, and physical integrity.
- Clocking, Power, and Sign-Off
- Implement CTS and drive skew, latency, and clock power optimization.
- Lead IR/EM sign-off strategy, thermal analysis, and full chip physical verification (DRC/LVS/ERC).
- Integrate and validate low power methodologies, including UPF/CPF flows.
- Cross-Functional Collaboration & Quality Ownership
- Partner with DFT and PD teams to ensure scan insertion, BIST structures, and test modes are physically robust and timing clean.
- Work with Packaging and SI teams on bump planning, floorplan constraints, and package-aware timing.
- Set physical design quality standards, conduct design reviews, and ensure flawless execution through tapeout.
- Leadership & Mentorship
- Provide technical leadership to a team of junior and mid-level physical designers.
- Mentor, coach, and guide engineers in methodology, debug, and best practices.
- Champion continuous improvement across flows, scripts, and design methodology.
Requirements
- 10+ years of relevant experience in ASIC Physical Design, with a strong track record of multiple tape-outs at advanced technology nodes (16nm → 3nm preferred).
- Deep expertise in: Floorplanning
- Place & Route
- CTS
- STA/Timing Closure
- Physical verification & sign-off
- Power integrity (IR drop/EM)
- Low power design and UPF
- Strong hands on proficiency with Cadence and/or Synopsys physical design toolchains.
- Solid understanding of RTL-to-GDS flows, design architecture trade-offs, and SoC integration complexities.
- Ability to translate product requirements into physical design goals, budgets, constraints, and deliverable plans.
- Strong communication skills—able to articulate technical decisions across cross-functional teams.
- Highly motivated, proactive, and able to operate effectively in a distributed team environment.
- Comfortable owning schedules, deliverables, and quality in a fast-moving development cycle.
- Exceptional analytical, debugging, and problem-solving skills with a meticulous attention to detail.
Benefits
- Competitive salaries
- Equity in the form of Incentive Stock Options (ISO)
- Employer paid medical insurance plan
- Health Savings Account (HSA) with employer contributions
- Dental and vision reimbursement account (HRA)
- 401(k) retirement plan with employer match
- Flexible work location with remote options
- Flexible time off
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
ASIC Physical DesignFloorplanningPlace & RouteClock Tree Synthesis (CTS)Static Timing Analysis (STA)Physical verificationPower integrityLow power designUPFGDSII
Soft skills
communication skillsleadershipmentorshipanalytical skillsproblem-solving skillsattention to detailproactivecollaborationquality ownershiptime management