Principal Technical Engineer, 3rd Party IP Engineer

Marvell Technology

Principal Technical Engineer responsible for 3rd party IP integration within Marvell’s semiconductor solutions. Engaging throughout SoC development and collaborating with IP providers for technology compliance.

Posted 7/28/2026full-timeMorrisville • Massachusetts, New York, North Carolina, Texas, Vermont • 🇺🇸 United StatesLead💰 $152,300 - $225,440 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in SoC development, including core requirements definition, IP integration, and silicon validation. Proficient in managing 3rd party developers and ensuring compliance with design rules and project management tasks.

Highest-signal resume keywords

SoC DevelopmentDDR Type InterfacesASIC Design FlowsProject ManagementDesign-for-Test Concepts

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SoC DevelopmentDDR Type InterfacesASIC Design FlowsLogic SynthesisPhysical DesignTiming AnalysisDRC/LVSFormal VerificationElectrical CheckingDesign-for-Test

Soft Skills

Communication SkillsCustomer Management

Tools & Technologies

3rd Party Developer Problem Reporting Tools

Industry Keywords

IP IntegrationSilicon ValidationCore DevelopmentTechnology ComplianceMulti-Chip Integrated Packaging

About the role

Key responsibilities & impact

work in parallel with a team of 3rd party IP engineers responsible for bringing in all subcontracted IP under the Marvell IP umbrella
involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation
assist sales in winning bids by working with leading edge IP providers to meet customer requirements
manage 3rd party developers in completing core designs and providing required design rules
advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider
post-silicon validation at customer sites will require a limited degree of travel
developing statements of work, leading provider progress reviews, using 3rd party developer problem reporting tools to drive to problem resolution
assist with 8D follow-through for significant supplier issues.

Requirements

What you’ll need

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging
Proficient in project management tasks required to manage 3rd party developers
Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking
Good understanding of Design-for-Test concepts including DFT logic insertion, test generation, scan and embedded core testing
Good communication and customer management skills.

Benefits

Comp & perks

employee stock purchase plan with a 2-year look back
family support programs to help balance work and home life
robust mental health resources to prioritize emotional well-being
recognition and service awards to celebrate contributions and milestones