Senior Staff Engineer – Digital IC Build Flow and Methodology

Marvell Technology

Senior Engineer specializing in scalable build scripts and front-end methodology for complex digital IC designs. Responsible for improving compilation, simulation, and regression flow across designs.

Posted 7/27/2026full-timeWestborough • California, Massachusetts, Texas • 🇺🇸 United StatesSenior💰 $151,000 - $223,440 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in ASIC/SoC design and verification, with strong programming skills in Python and familiarity with EDA toolchains. Proven ability to design and optimize build flows, enhance CI processes, and collaborate effectively across teams.

Highest-signal resume keywords

ASIC/SoC DesignPython ProgrammingBuild System OptimizationEDA Toolchain IntegrationCollaboration Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

PythonTCLC/C++Shell ScriptingBuild ScriptsDependency AnalysisIncremental BuildsFlow OptimizationFront-End Design FlowsDebugging Infrastructure Issues

Soft Skills

Problem-SolvingCollaboration

Tools & Technologies

EDA ToolsCI ToolsBuild Systems

Certifications & Qualifications

Bachelor’s Degree in Electrical EngineeringMaster’s Degree in Electrical Engineering

Industry Keywords

Chip DesignVerification FlowsMethodology StandardsSimulationRegression Workflows

Tech Stack

Tools & technologies

PythonShell Scripting

About the role

Key responsibilities & impact

Design, implement, and maintain chip design build flows supporting block, subsystem, full-chip, and multi-chip simulations
Develop and own build scripts and orchestration logic for compile, elaborate, simulate, and regression workflows
Improve build performance through dependency analysis, incremental builds, caching, and flow optimization
Define and evolve methodology standards for front-end design and verification flows
Architect and enhance CI / pre-submit verification flows to improve quality and turnaround time
Integrate and support industry EDA tools within robust scripted flows
Collaborate with RTL, DV, methodology, and infrastructure teams
Debug complex infrastructure and build-system issues
Drive adoption through documentation and training

Requirements

What you’ll need

Bachelor’s or Master’s degrees in electrical engineering, Computer Engineering, Computer Science, or related field
8+ years of experience in ASIC/SoC design, verification, or methodology roles
Strong programming skills in Python and at least one of TCL, C/C++, or shell scripting
Experience with make-based or graph-based build systems
Understanding of front-end chip design flows
Experience debugging large-scale infrastructure issues
Familiarity with EDA toolchains
Strong problem-solving and collaboration skills

Benefits

Comp & perks

employee stock purchase plan with a 2-year look back
family support programs to help balance work and home life
robust mental health resources to prioritize emotional well-being
recognition and service awards to celebrate contributions and milestones