
Senior to Staff Engineer, Design Verification
Marvell Technology
full-time
Posted on:
Location Type: Office
Location: DaNang • 🇻🇳 Vietnam
Visit company websiteJob Level
Senior
Tech Stack
LinuxPerlPython
About the role
- Analyze the and extract Spec, create comprehensive test plan and coverage plan.
- Contribute to the development of UVM components, ENV, Coverage model, and Assertion protocol checkers
- Develop testing strategies to achieve coverage
- Run simulation, and regression, debug and propose bug fixings for both DV/C model
- Merge, analyze and improve the coverage results.
- Run GLN/SDF simulation and propose ECO fixings.
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 2-7 years of related professional experience
- Or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 1-5 years of experience.
- Experience with Verilog and SystemVerilog, preferably with UVM.
- Skilled in C and C++ programming languages
- Knowledge of Digital Signal Processing (DSP) theory and practical experience is a plus
- Experience with scripting languages, e.g., Python or Perl
- Working knowledge of the Linux operating system
- English Proficiency
Benefits
- Competitive salary, plus 13th-month salary and performance-based bonus
- RSUs (Restricted Stock Units) for new joiners and on-going annually
- Premium health & accident insurance for you and your family (spouse and children)
- Annual medical check-up at a designated hospital arranged by Marvell
- Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays
- Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more.
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
VerilogSystemVerilogUVMCC++Digital Signal ProcessingPythonPerlLinuxtest plan development
Certifications
Bachelor’s degreeMaster’s degreePhD