Senior Staff Engineer, ASIC Design, Implementation, LEC, STA, Power Analysis

Marvell Technology

Timing/STA Engineer responsible for ASIC design and implementation at Marvell, focusing on advanced timing methodologies and STA signoff. Collaborate with cross-functional teams to optimize high-speed designs.

Posted 5/24/2026full-timeIrvine • California • 🇺🇸 United StatesSenior💰 $135,900 - $201,130 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Develop and validate timing constraints for intricate SoC designs
Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for STA signoff
Own and contribute to various STA related tasks like doing timing ECOs for blocks and SoCs, developing custom scripts to create histograms, STA flow management, etc.
Perform static timing analysis (STA) using industry-standard tools (e.g. Primetime)
Define and implement timing signoff methodologies, including process corners, derates, and uncertainties
Resolve or find workarounds for tool issues, independently or working with EDA tool vendors
Conduct post-route timing checks and quality of results (QoR) analysis
Automate STA related processes/flow using scripting languages such as Tcl or Python
Create QoR dashboards, histograms for STA runs across all modes
Ensure compliance with timing signoff checklists and criteria
Document best practices and lessons learned to drive continuous improvements in future projects.

Requirements

What you’ll need

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience
Minimum of 5 years of industry experience in ASIC timing and STA
Strong understanding of ASIC design flows, from RTL to GDSII
Knowledge and hands-on experience with STA methodologies and implementation
Proficiency in using STA tools and scripting languages (e.g., Tcl, Perl)
Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5
Strong understanding of timing constraint development for hierarchical designs, timing ECO creation and final timing signoff
Familiarity with physical design and timing optimization techniques and strategies to achieve deterministic timing closure
Proven track record of delivering successful designs on time and meeting performance, power and area goals
Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues
Strong communication and collaboration skills to work effectively within cross-functional teams.

Benefits

Comp & perks

Employee stock purchase plan with a 2-year look back
Family support programs to help balance work and home life
Robust mental health resources to prioritize emotional well-being
Recognition and service awards to celebrate contributions and milestones

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

static timing analysistiming ECOstiming signoff methodologiestiming constraint developmenttiming optimization techniquesscripting languagesASIC design flowsQoR analysistiming complexitiesEDA tools

Soft Skills

problem-solvingattention to detailcommunicationcollaborationanalytical skills

Certifications

Bachelor’s degree in Computer ScienceBachelor’s degree in Electrical EngineeringMaster’s degree in Computer ScienceMaster’s degree in Electrical EngineeringPhD in Computer SciencePhD in Electrical Engineering