Senior Staff Engineer, ASIC/VLSI Synthesis and Design

Marvell Technology

Join Marvell as a Senior Staff Engineer specializing in ASIC/VLSI synthesis and design. Focus on timing constraints and collaborate cross-functionally to drive ASIC implementation.

Posted 5/22/2026full-timeIrvine • California • 🇺🇸 United StatesSenior💰 $135,900 - $201,130 per yearWebsite

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Develop and validate timing constraints for intricate SoC designs
Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows
Own and contribute to various Front-End Implementation tasks & flows like Synthesis, UPF development, Logical Equivalence Checks (LEC), Functional ECOs, etc.
Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows
Perform Physical Aware Synthesis using industry-standard tools like Fusion Compiler
Resolve or find workarounds for tool issues, independently or working with EDA tool vendors
Automate Front End Flows and processes using scripting languages such as Tcl or Python
Ensure compliance with Netlist Handoff checklists and criteria for delivery to PD
Document best practices and lessons learned to drive continuous improvements in future projects

Requirements

What you’ll need

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience
Minimum of 5 years of industry experience in ASIC implementation and synthesis
Strong understanding of ASIC design flows, from RTL to GDSII
Knowledge and hands-on experience with synthesis and STA methodologies and implementation
Proficiency in using synthesis tools, STA tools, and scripting languages (e.g., Tcl, Perl)
Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5
Strong understanding of timing constraint development for hierarchical designs
Experience doing functional ECOs using industry standard tools and flows like Conformal ECO
Experience with UPF development for blocks and SoCs
UPF validation using tools like Conformal Low Power (CLP)
Familiarity with physical design and timing optimization techniques and strategies to achieve timing closure
Proven track record of delivering successful designs on time and meeting performance, power and area goals
Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues
Strong communication and collaboration skills to work effectively within cross-functional teams.

Benefits

Comp & perks

employee stock purchase plan with a 2-year look back
family support programs
robust mental health resources
recognition and service awards

ATS Keywords

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Hard Skills & Tools

ASIC implementationsynthesistiming analysistiming constraint developmentphysical aware synthesisscripting (Tcl, Python)functional ECOsUPF developmentlogical equivalence checks (LEC)timing optimization

Soft Skills

problem-solvingattention to detailanalytical skillscommunicationcollaboration