Senior Staff Design Verification Engineer – PCIE/CXL Sub-System

Marvell Technology

Senior Staff Design Verification Engineer at Marvell designing and verifying PCIe and CXL subsystems. Collaborating with teams to ensure compliance and high performance for advanced custom chips.

Posted 5/22/2026full-timeIrvine • California • 🇺🇸 United StatesSenior💰 $135,900 - $201,130 per yearWebsite

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems, from test planning through coverage closure and signoff
Define and execute comprehensive verification plans based on protocol specifications and micro-architecture requirements
Architect and develop scalable UVM/System Verilog testbenches for PCIe/CXL controllers and fabric-level subsystems
Integrate and configure PCIe/CXL VIP for subsystem and system-level verification environments
Validate CXL.io, CXL.cache, and CXL.mem protocols, including coherency and memory semantics across complex flows
Develop constrained-random and directed test suites to achieve high functional coverage across corner and stress scenarios
Debug complex failures such as protocol violations, ordering issues, and coherency bugs using waveforms, logs, and protocol analyzers
Implement System Verilog Assertions (SVA) for protocol compliance, improving early bug detection and debug efficiency
Drive functional, code, and assertion coverage closure, identifying gaps and developing targeted tests to meet signoff goals
Validate performance metrics (latency, throughput, QoS) under high-bandwidth and stress workloads
Develop automation (Python/Shell) for regression management, log triage, and coverage reporting, improving productivity
Collaborate with design, architecture, firmware and validation teams, influencing design-for-verification and mentoring junior engineers

Requirements

What you’ll need

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field
5-10 years of experience in ASIC/SoC verification
Strong knowledge of PCIE and CXL protocols and architecture
Expertise in System Verilog and UVM methodology
Experience with debugging complex verification issues
Familiarity with industry-standard tools (e.g., simulation, waveform debugging, coverage tools)

Benefits

Comp & perks

Employee stock purchase plan with a 2-year look back
Family support programs to help balance work and home life
Robust mental health resources to prioritize emotional well-being
Recognition and service awards to celebrate contributions and milestones

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

PCIeCXLUVMSystem Verilogtest planningverification planstestbenchesSystem Verilog Assertionsautomationdebugging

Soft Skills

collaborationmentoringinfluencing