Principal Digital IC Design Engineer
Marvell Technology
full-time
Posted on:
Location Type: Office
Location: Boise • Idaho • Texas • United States
Visit company websiteExplore more
Job Level
About the role
- Define and drive micro-architecture and RTL implementation for complex functional blocks in custom AI accelerators, CPUs, or high-speed interconnect silicon, working in advanced process nodes (3nm, 2nm) to meet aggressive performance, power, and area (PPA) targets
- Own end-to-end delivery of assigned blocks or subsystems from architecture definition through tape-out, including synthesis, timing closure, formal verification, and physical verification sign-off
- Collaborate closely with cross-functional teams including verification engineers on test plan development and coverage analysis, physical design teams on floorplanning and timing optimization, and DFT teams on scan insertion and test pattern generation
- Drive timing and power closure for high-speed designs (>1 GHz), working with implementation teams to resolve congestion issues, develop timing ECOs, and optimize critical paths to achieve sign-off quality
- Partner with customer architects and engineers to translate application requirements into hardware specifications, participate in design reviews, and support technical discussions throughout the development cycle
- Integrate and validate third-party IP (PCIe, CXL, DDR, SerDes, etc.) within the SoC, ensuring interoperability and compliance with industry standards while meeting customer-specific performance requirements
- Support post-silicon validation and bring-up activities, including debugging silicon issues, correlating RTL simulations with lab measurements, and working with validation teams to resolve production issues
- Contribute to methodology development by improving design flows, developing automation scripts, and establishing best practices that enhance productivity across global design teams
- Present technical work and design trade-offs to stakeholders through design reviews, architecture discussions, and cross-functional team meetings, maintaining clear documentation throughout the development cycle
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 10+ years of professional experience in digital IC design, OR Master's degree with 5+ years of experience
- Proven RTL design experience with expertise in synthesis, static timing analysis and closure, formal verification, and gate-level simulations
- Proficiency with design quality checks including Lint, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and logic equivalence checking (LEC)
- Strong foundation in modern SoC architectures and industry-standard interface protocols including AXI, DDR, Ethernet, and PCIe
- Experience with low-power design methodologies including clock gating, power gating, and UPF (Unified Power Format) implementation
- Hands-on experience with the full chip development lifecycle, from micro-architecture definition through physical implementation
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
RTL designsynthesisstatic timing analysisformal verificationgate-level simulationsdesign quality checkslow-power design methodologiesmicro-architecture definitionphysical implementationtiming closure
Soft Skills
collaborationcommunicationproblem-solvingpresentation skillsdocumentation