Senior Staff Design Verification Engineer
Marvell Technology
full-time
Posted on:
Location Type: Hybrid
Location: Austin • Idaho • Texas • United States
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Job Level
Tech Stack
About the role
- Define and drive comprehensive verification strategies and test plans for complex SoCs, subsystems, or IP blocks in custom AI accelerators, CPUs, or high-speed interconnect silicon built in advanced process nodes (3nm, 2nm)
- Architect and implement sophisticated UVM-based verification environments including testbenches, reference models, scoreboards, monitors, coverage models, and protocol checkers to ensure exhaustive verification of assigned blocks
- Develop and execute comprehensive test plans encompassing directed tests, constrained-random scenarios, and coverage-driven verification to verify functional correctness, performance requirements, and error handling across all design features
- Own end-to-end verification closure including code coverage, functional coverage, and assertion coverage analysis, working with design teams to resolve coverage gaps and achieve 100% coverage goals with documented waivers
- Debug complex simulation failures using systematic root-cause analysis techniques, correlating RTL behavior with specifications, and partnering with designers to identify and resolve design issues efficiently
- Collaborate closely with logic designers, architects, DFT engineers, and physical design teams throughout the development cycle on micro-architecture reviews, test plan development, timing closure support, and gate-level simulation execution
- Drive verification methodology improvements by developing reusable verification components (VKITs), creating automation scripts for regression management and coverage analysis, and establishing best practices that enhance productivity across global verification teams
- Support multiple verification platforms including RTL simulation, emulation/FPGA prototyping, and post-silicon validation, ensuring test portability and maintaining verification infrastructure across platforms
- Integrate and validate third-party VIPs (Verification IP) and vendor models for industry-standard protocols, ensuring proper configuration and effective utilization within the verification environment
- Present verification progress, coverage results, and quality metrics to stakeholders through milestone reviews, cross-functional design reviews, and verification sign-off meetings, maintaining clear documentation throughout the verification cycle
- Coach and mentor junior verification engineers when necessary to develop their technical skills and achieve successful project outcomes
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 5+ years of professional experience in ASIC/SoC verification, OR Master's degree and/or PhD with 3+ years of experience
- Strong background in SoC verification and UVM-based testbench development using SystemVerilog, with proven experience architecting and implementing constrained-random verification environments
- Deep understanding of verification methodology including object-oriented programming, coverage-driven verification closure, directed and randomized testing strategies, and assertion-based verification
- Hands-on experience with industry-standard simulation tools including Synopsys VCS, Cadence Incisive/Xcelium, or Mentor Questa for RTL and gate-level verification
- Strong scripting skills in Python, Perl, Tcl, or shell scripting for test automation, regression management, coverage analysis, and verification flow development
- Experience with the full verification lifecycle from test plan development through coverage closure, working across multiple verification platforms (simulation, emulation, post-silicon)
- Solid understanding of modern SoC architectures, industry-standard interfaces and protocols including AXI, AHB, PCIe, CXL, DDR/LPDDR, and high-speed SerDes
- Proven ability to work independently with minimal supervision while managing multiple priorities and meeting aggressive project schedules
- Excellent written and verbal communication skills with ability to present verification strategies and results to cross-functional teams including architecture, design, DFT, and physical design
- Strong interpersonal skills and demonstrated ability to work collaboratively in a matrix organization across global design centers and time zones
- Demonstrated problem-solving and critical thinking skills with ability to debug complex simulation failures and develop innovative solutions to verification challenges
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills & Tools
SoC verificationUVM-based testbench developmentSystemVerilogconstrained-random verificationcoverage-driven verificationassertion-based verificationPythonPerlTclRTL simulation
Soft Skills
problem-solvingcritical thinkingcommunicationcollaborationmentoringindependencetime managementpresentation skillsinterpersonal skillsorganizational skills