implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs
running Tessent tools for insertion of all DFT structures
enhancing DFT methodologies and tools
chiplet DFT solutions, including Tessent SSN
definition of STA constraints, pattern generation & post-silicon bring-up and debug
mentoring, guiding, and driving a small team of DFT engineers

Requirements

Bachelor’s, Master’s degree or PhD in Computer Science, Electrical Engineering or related fields
minimum of 10 years of work experience
Direct DFT experience with at least 8 years in the custom chip (ASIC) design business
Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug
Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design
Strong fundamentals in digital circuit design and logic design
Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC)
Proven track record of problem solving and innovation to meet challenging design requirements
Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion
Excellent communications skills both verbal and written
Scripting skills using Python, PERL, Tcl and C-Shell is plus.

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

DFTASIC designSCANMBISTValidationSTAIP-DFXPost-Silicon Bring-upDebugdigital circuit design

Soft Skills

mentoringguidingproblem solvinginnovationteam playercommunication

Certifications

Bachelor’s degreeMaster’s degreePhD