Senior Staff System & Modeling Engineer – Wireline Communications
Marvell Technology
full-time
Posted on:
Location Type: Office
Location: Santa Clara • California • 🇺🇸 United States
Visit company websiteSalary
💰 $140,350 - $210,200 per year
Job Level
Senior
Tech Stack
Python
About the role
- Architect and model end-to-end wireline communication systems using MATLAB, Simulink, SystemVerilog, C/C++, and Python to support modeling, verification, and architectural exploration
- Devise novel DSP techniques to push the envelope of performance for ultra-high-speed wireline systems
- Develop models that accurately capture performance, interface characteristics, and key non-idealities or impairments (e.g., bandwidth limitations, jitter, noise, distortion) of key analog blocks
- Collaborate closely with other system architects to explore design trade-offs, validate architectural assumptions, and refine system-level specifications
- Model analog and mixed-signal circuit blocks (e.g., CTLEs, ADCs, PLLs, TX/RX front-ends) using SystemVerilog or other HDLs to support functional design verification and system-level integration
- Work with analog designers and signal integrity engineers to ensure model fidelity and alignment with physical implementation
- Support lab testing and debugging of prototype systems and silicon bring-up
- Mentor junior engineers and provide technical leadership across modeling and verification efforts
- Author technical documentation, modeling guidelines, and contribute to customer-facing deliverables
Requirements
- PhD or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- 5-10+ years of experience in system modeling and analog abstraction for wireline communication systems
- Solid knowledge of DSP techniques for ultra-high speed wireline systems
- Solid knowledge of equalization techniques used in wireline channels, including Continuous-Time Linear Equalizers (CTLE), Feed-Forward Equalizers (FFE), and Decision Feedback Equalizers (DFE)
- Very good understanding of analog and mixed-signal circuit behavior and abstraction techniques
- Experience with SerDes standards such as PCI Express (PCIe), Universal Chiplet Interconnect Express (UCIe), or other high-speed interconnect protocols
- Excellent problem-solving and analytical skills
- Strong communication and collaboration abilities
- Strong proficiency in System Verilog, Verilog, MATLAB, Simulink, C/C++, Python, and scripting tools
Benefits
- Employee stock purchase plan with a 2-year look back
- Family support programs to help balance work and home life
- Robust mental health resources to prioritize emotional well-being
- Recognition and service awards to celebrate contributions and milestones
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
MATLABSimulinkSystemVerilogC/C++PythonDSP techniquesanalog circuit modelingmixed-signal circuit modelingequalization techniquesSerDes standards
Soft skills
problem-solvinganalytical skillscommunicationcollaborationmentoringtechnical leadership
Certifications
PhD in Electrical EngineeringMaster’s degree in Electrical Engineering