Senior Verification Engineer
Marvell Technology
full-time
Posted on:
Location Type: Office
Location: Petah-Tikva • 🇮🇱 Israel
Visit company websiteJob Level
Senior
About the role
- Develop and maintain advanced verification components, environments, and testbenches
- Build System Verilog UVM verification environments for units in CnM
- Apply coverage-driven verification techniques, constrained random testing, and object-oriented programming
- Deliver the IPs to higher level verification like Cluster, FC and emulation
Requirements
- B.Sc. or M.Sc. in Electrical or Computer Engineering
- 4+ years of hands-on experience in ASIC/RTL verification
- Experience in SystemVerilog and UVM methodology
- Good understanding of coverage-driven verification and OOP principles
- Excellent problem-solving and self-learning abilities
- Good interpersonal skills and a teamwork
Benefits
- competitive compensation
- great benefits
- shared collaboration
- transparency
- inclusivity
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
SystemVerilogUVMcoverage-driven verificationconstrained random testingobject-oriented programmingASIC verificationRTL verification
Soft skills
problem-solvingself-learninginterpersonal skillsteamwork
Certifications
B.Sc. in Electrical EngineeringM.Sc. in Computer Engineering