FPGA Design Engineer Intern
Leonardo DRS
internship
Posted on:
Location Type: Office
Location: Dallas • Texas • 🇺🇸 United States
Visit company websiteJob Level
Entry Level
Tech Stack
Linux
About the role
- Support architecture tradeoff projects
- Participate in RTL coding and test bench development
- Contribute in FPGA design flows for synthesis, place and route, timing closure, and design verification testing
Requirements
- Enrolled in an Undergraduate or Master's degree in Computer Engineering, or Electrical Engineering or related field with at least at 3.0 GPA
- Be available to work full-time (40 hours per week) for at least 10 weeks during Summer 2026 at the DRS Dallas facility
- U.S. Citizenship status is required as this position will require the ability to access US only data systems
- Knowledge of Windows/Linux OS
Benefits
- medical, dental, and vision coverage
- company contribution to a health savings account
- telemedicine
- life and disability insurance
- legal insurance
- 401(k) savings plan
- wellness programs that focus on physical, emotional, and financial well-being
- flexible work schedules with our 9/80 program
- competitive vacation
- health/emergency leave
- paid parental leave
- community service hours
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
RTL codingtest bench developmentFPGA designsynthesisplace and routetiming closuredesign verification testing