Derive engineering specifications from system requirements and develop detailed architecture.
Plan and execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint).
Generate test plans.
Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards.
Silicon/FPGA bring up, characterization and production ramp/support/collateral.

Requirements

Bachelor’s degree in Electrical Engineering or equivalent degree
minimum 6 years of prior relevant experience (or Master’s degree plus 4 years of prior relevant experience)
active SECRET Clearance
Proficiency in mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs
Proficient in VHDL design process and FPGA flow
Knowledge of Ethernet, TCP/IP protocols
Strong logic/board debug, and analytical skills
Excellent written, verbal, and presentation skills.

Benefits

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

RTLHLSC++VHDLFPGAsynthesisSTALinuxtest plansmapping algorithms

Soft Skills

analytical skillswritten communicationverbal communicationpresentation skillsdebugging skills

Certifications

Bachelor’s degree in Electrical EngineeringMaster’s degreeactive SECRET Clearance