ASIC/FPGA Design Engineer – SMES
L3Harris Technologies
full-time
Posted on:
Location Type: Office
Location: Camden • New Jersey • 🇺🇸 United States
Visit company websiteSalary
💰 $111,515 - $151,500 per year
Job Level
Mid-LevelSenior
Tech Stack
LinuxTCP/IP
About the role
- Responsible for deriving engineering specifications from system requirements and developing detailed architecture
- Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
- Generate test plans
- Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
- Silicon/FPGA bring up, characterization and production ramp/support/collateral
Requirements
- BSEE, MSEE Preferred
- 5+ year’s equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
- Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
- Proficient with CDC, RDC. Formal EDA.
- Proficient in VHDL.
- Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
- Strong logic/board debug, and analytical skills.
- Experience with project leadership and EVM
- Excellent written, verbal, and presentation skills.
- Active SECRET Clearance Preferred
Benefits
- health insurance
- disability insurance
- 401(k) match
- flexible spending accounts
- EAP
- education assistance
- parental leave
- paid time off
- company-paid holidays
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
RTL designHLSC++RTL qualityRDCCDCFormal EDAVHDLSynthesisPAR
Soft skills
analytical skillsproject leadershipcommunication skillspresentation skillswritten skillsverbal skills
Certifications
BSEEMSEESECRET Clearance