STA/Timing Engineer, Digital PD
Kandou
full-time
Posted on:
Location Type: Hybrid
Location: Dortmund • Germany
Visit company websiteExplore more
Tech Stack
About the role
- Work closely with the Architecture and RTL (frontend) team to ensure first-time-right high-volume silicon production Timing Constraints development
- Timing constraints validation, sign-off Static Timing Analysis and support for full chip & block-level timing closure
- Block and chip level STA with all aspects, reviewing and defining constraints with the design team
- Implementing SDC constraints to be used for block and chip (flat) STA
- Analyze violations and clean with help of frontend design, DFT and physical design team
- Participate in developing improvements to scripts/methodologies/flows with focus on SDC and STA signoff analysis
- Interact closely with the design team to understand requirements and implement solutions for STA
- Support IP and chip level integration
Requirements
- 10+ years’ experience in the semiconductor industry, with min. 3yrs in a technical Digital STA and Timing Signoff role.
- Good knowledge of basic RTL to GDS implementation flow (synthesis, P&R, LEC, STA)
- Substantiated experience in gathering and defining SDC constraints, specifically on top-level incl. DFT.
- Good scripting capabilities (shell, TCL, Python, make) and good understanding of data management (revision control system)
- Expertise in Timing/SDC constraints generation and management.
- Expertise in running hierarchical and flat static timing analysis incl. cross talk SI/glitch analysis.
Benefits
- Flexible work arrangements
- Professional development opportunities
Applicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard skills
Static Timing AnalysisSDC constraintsDigital STATiming SignoffRTL to GDS implementationsynthesisplace and route (P&R)logic equivalence checking (LEC)scripting (shell, TCL, Python, make)cross talk SI/glitch analysis