Kandou

Architect

• Write and own content of specifications at chip, block, and interface level.
• Participate in standards bodies and represent company interests in those bodies.
• Work on cross-functional teams to implement improvement actions to optimise design cost, quality and/or schedule as appropriate.
• Responsibility for digital design and debug of assigned logic blocks (when appropriate).

Digital System Architect

Engineer

• Implement, document, and maintain software for system-level modelling of serial communication links in MATLAB, Python, and C++
• Work closely with system architects in order to budget the link and define block-level specs of the transceiver
• Work closely with analog, digital, and verification teams in order to support the design and verification process

Modeling Engineer

• Work closely with the Architecture and RTL (frontend) team to ensure first-time-right high-volume silicon production Timing Constraints development
• Timing constraints validation, sign-off Static Timing Analysis and support for full chip & block-level timing closure
• Block and chip level STA with all aspects, reviewing and defining constraints with the design team
• Implementing SDC constraints to be used for block and chip (flat) STA
• Analyze violations and clean with help of frontend design, DFT and physical design team
• Participate in developing improvements to scripts/methodologies/flows with focus on SDC and STA signoff analysis
• Interact closely with the design team to understand requirements and implement solutions for STA
• Support IP and chip level integration

Digital System Architect

Modeling Engineer

STA/Timing Engineer, Digital PD