Kandou

Full-stack Engineer

• Lead the SI/PI function at Kandou AI, defining methodologies, best practices, and technical direction
• Partner with technology and product teams to guide SI/PI architecture and resolve system-level challenges
• Work closely with circuit designers to ensure robust SI/PI implementation in silicon
• Engage with customers and suppliers to define and validate hardware solutions (packages, PCB/backplane layouts, materials, interposers, connectors) for Kandou products
• Perform and lead theoretical and simulation-based SI analysis of products, channels, test structures, and system implementations
• Prepare and communicate technical analyses and recommendations to internal teams and external stakeholders
• Evaluate and benchmark signaling schemes (e.g., Chord signaling, PAM) in terms of SI/PI performance, power, and implementation trade-offs
• Drive SI/PI and power delivery solutions for packages and evaluation platforms in collaboration with design teams
• Collaborate with system architects to define and extract channel specifications and requirements

Signal Integrity Lead Engineer

Hardware Engineer

• Develop embedded firmware for PCIe products
• Collaborate with cross-functional teams to architect and verify HW-SW interfaces
• Utilize C/C++ and Python for firmware and SDK development
• Work on high-speed interface products in Data Center environments

Firmware Engineer Lead

• Work to develop, test and maintain embedded firmware for silicon products.
• Ensuring the robustness of code by implementing and running a software test suite
• Migration, consolidation and development of existing silicon debug software
• Software design and support for our silicon design infrastructure

Firmware Engineer, Bare Metal

Business Development Rep

• Represent Kandou in its sales and business development activities for [the assigned region]
• Provide management with communications from potential customers including new opportunities, competitive threats and general customer commercial and technical news as relevant
• Inform customers and potential customers terms on which products and/or services could be provided by Kandou
• Provide product information requested by customers and potential customers of Kandou
• Provide guidance and leadership on building the [named region] business development team to support customer demand
• Lead the account team on all aspects of delivering a positive Kandou experience for customers

Business Development Manager

Mechanical Engineer

• Work closely with the Architecture, RTL, DFT teams to ensure first-time-right high-volume silicon production
• Timing constraints improvement and timing constraints validation, signoff
• Static Timing Analysis and block-level timing closure
• Synthesis, block level floor-planning, power grid design, place & route, clock tree synthesis, electromigration / IR-Drop analysis, power/signal integrity analysis, crosstalk analysis, formal equivalence checking and physical verification (DRC / LVS / Antenna)
• Participate in developing improvements to scripts/methodologies/flows
• Interact closely with the design team to understand requirements and implement solutions as also helping on providing design views for use with digital PD flows (LIB, LEF, DEF, GDS, SPEF, etc.)
• Support IP and chip level integration
• Support and interact with customers on requirements and IP delivery
• Manage workload and schedule and report to internal management team

Physical Design Engineer

• Define digital architecture concepts and specify analog-to-digital interfaces.
• Develop RTL for high-speed digital blocks and contribute to IP verification and basic DFT implementation.
• Perform logic synthesis and support timing analysis activities.
• Design and verify high-performance digital circuits meeting area, timing, and power requirements.
• Develop block-level specifications based on system-level requirements.
• Collaborate closely with verification, physical implementation, and analog/mixed-signal engineering teams.
• Analyse and implement high-speed serial protocols (e.g., USB4, PCIe).
• Support post-silicon bring-up, debugging, characterization, and productization.
• Validate and test silicon in laboratory environments.

Digital Design Engineer

• Join Kandou to redefine the economics of AI infrastructure.
• Leverage proprietary MIMO-over-copper technology for AI memory fabric.
• Create scalable and energy-efficient solutions for AI training and inference.
• Collaborate with engineering teams in Hyderabad or Bangalore.

Software Engineer – 2 openings

• Complete all Package design activities within the given time frame as defined by the project deliverables
• Complete Package design review processes with the Assembly subcons to ensure no design rule violations
• Liaise closely with the respective IC layout Engineers during Package design phase
• Complete verification of Electrical characteristics of the package and unit design using available SW Tools
• Ensure cost effective methodologies are incorporated into Kandou’s BGA substrate and LF designs (Multi Layer / Mechanical Drill / Plating Lines etc)
• Provide support, guidance and instructions to Assembly / Package related activities, questions and issues
• Present detailed weekly reports of activities and progress to the cross-functional team
• Work with multi-functional groups including product design, engineering and marketing to ensure our package design/technology requirements are fully supported by Kandou’s assembly partners

Package Design Engineer

Lead Software Engineer, Firmware

Engineer

• Hierarchical MBIST and scan insertion, BSD implementation ATPG pattern generation, coverage analysis, converging to high coverage metrics
• Pattern simulations with timing
• Defining test mode timing constraints, analyzing the timing reports and converge timing
• Developing cycle accurate functional patterns using IJTAG methodology
• Closely working with the test and production engineering teams to debug and bring up devices at probe and final test
• Debugging silicon issues

DFT Engineer

• Implement, document, and maintain software for system-level modelling of serial communication links in MATLAB, Python, and C++
• Work closely with system architects in order to budget the link and define block-level specs of the transceiver
• Work closely with analog, digital, and verification teams in order to support the design and verification process

Modeling Engineer

• Develop design verification methodologies and implement standard debug flows
• Work with designers in verification and validation of circuit designs
• Participate in design reviews
• Prepare design verification plan based on design specifications
• Plan and schedule assigned projects for timely completion
• Utilize the latest techniques, tools, and technologies for design verification activities
• Maintain design verification environment and track & close design bugs

Digital Verification Engineer

• Will be a key member of a small FPGA team that will own prototyping of Kandou’s architectures in FPGA
• Will need to work independently with low day-to-day supervision and own FPGA projects
• Will work with Kandou’s architecture and system software teams on FPGA prototyping and participate in the entire lifecycle of project including support.
• Will participate in technical discussions with IP providers and be responsible for driving some of them.

FPGA Design Engineer

IT Support

• Help in design, setting up, operating and maintaining datacenter and office networks
• Improve reliability and optimize performance of network infrastructure: datacenters, office networks, lab networks, site-to-site VPN
• Debugging help in user support cases, prioritizing production impacting cases
• Maintain documentation