ASIC Physical Design Engineer

K2 Space Corporation

full-time

Posted on: 4/13/2026

Location Type: Remote

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💰 $130,000 - $200,000 per year

About the role

Execute the complete physical design flow for complex SoC blocks and/or top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
Collaborate with DFT teams to ensure clean timing convergence.
Develop and maintain scripts and automation to improve flow efficiency and consistency.
Support physical sign-off activities including DRC/LVS, STA, EM, Signal Integrity and power analysis.
Assist in chip-level integration, timing and functional ECOs, and tapeout preparation.
Contribute to methodology development, tool evaluation, and flow documentation.

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
2+ years of experience in ASIC physical design for complex SoCs.
Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
Strong understanding of timing analysis, power optimization, and physical verification flows.
Experience with hierarchical or flat SoC design methodologies.
Familiarity with FinFET technologies.
Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Benefits

Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, paid parental leave, and many other perks

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills & Tools

physical design flowsynthesisfloorplanningplace & routeCTSSTAphysical verificationtiming closurepower optimizationDFT

Soft Skills

problem-solvingcollaborationcross-functional teamwork