Research Engineer – System Technology, PhD Intern

Intel Corporation

PhD research intern advancing Intel semiconductor packaging and STCO methodologies. Evaluating 2.5D/3D integration schemes for memory and logic stacking.

Posted 9/3/2026internshipHillsboro • California, Oregon, Texas • 🇺🇸 United StatesEntry Level💰 $141,998 - $142,002 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in System Technology Co-optimization methodologies and system architecture modeling, with a strong foundation in digital circuit analysis, VLSI physical layout, and electronic design automation. Proficient in IC design and familiar with advanced packaging technologies, contributing to innovative semiconductor solutions.

Highest-signal resume keywords

Ph.D. Candidacy In Electrical EngineeringSystem Architecture ModelingDigital Circuit Analysis And DesignIC Design And Physical LayoutFamiliarity With Cadence Virtuoso

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

System Technology Co-optimizationDigital Circuit AnalysisVLSI Physical LayoutElectronic Design Automation3DIC Design And SimulationProgramming In PythonMulti-Physics ModelingIC DesignTape-Out Experience3D/2.5D Packaging Technologies

Soft Skills

CollaborationInnovation Drive

Tools & Technologies

Cadence VirtuosoSynopsys Fusion Compiler

Industry Keywords

Semiconductor ProcessingIntegrated Circuit ManufacturingDRAM Circuit DesignSRAM Circuit Design

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Develop and enhance System Technology Co-optimization (STCO) methodologies
Perform system-level evaluations of novel devices, interconnects, patterning, materials, systems, and integration schemes
Evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking across product architectures
Collaborate with diverse teams to drive innovation across various applications
Contribute to Intel's semiconductor processing and packaging roadmap

Requirements

What you’ll need

Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design, or similar
1–2+ years of relevant research experience in system architecture modelling, digital circuit analysis and design, VLSI physical layout, electronic design automation, or multi-physics modeling of electronic materials or systems
Familiarity with IC design and physical layout tools such as Cadence Virtuoso or Synopsys Fusion Compiler
Preferred: System architecture design and modelling
Preferred: IC design, simulation, physical layout, and tape-out experience
Preferred: Familiarity with DRAM and SRAM circuit design and layout
Preferred: Familiarity with integrated circuit manufacturing flow and requirements
Preferred: Familiarity with 2.5D and 3D packaging technologies
Preferred: 3DIC design and simulation experience
Preferred: Good programming skills, preferably in Python

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health benefits
Retirement benefits
Vacation benefits
Hybrid work model allowing employees to split time between working on-site and off-site
Hands-on experience with cutting-edge technologies
Collaboration with industry leaders and innovators