Principal Engineer, Mixed Signal Logic Design

Intel Corporation

Principal Engineer developing mixed signal logic designs for Intel's high-speed IPs. Leading the architecture definition and verification of integrated IP blocks with a focus on performance and power.

Posted 6/25/2026full-timeFolsom • California • 🇺🇸 United StatesLead💰 $220,920 - $311,890 per yearWebsite

About the role

Key responsibilities & impact

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or high-speed IPs
Participates in the definition of architecture and microarchitecture features of the block being designed
Applies various strategies, tools, and methods to write RTL and optimize logic
Reviews the verification plan and implementation to ensure design features are verified correctly
Supports SoC customers to ensure high-quality integration of the IP block
Acts as a change agent and role model for Intel values

Requirements

What you’ll need

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related STEM field with 12+ years of relevant experience
Proficiency in System Verilog, including experience with OVM/UVM methodologies
Demonstrated experience in developing IP or SoC verification environments, writing validation plans, and executing test cases

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health insurance
Retirement plans
Vacation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

RTL codingSystem VerilogOVMUVMIP developmentSoC verificationvalidation planstest case executionlogic designsimulation

Soft Skills

leadershipcommunicationchange agentrole model

Certifications

Bachelor's degree in Computer ScienceBachelor's degree in Computer EngineeringBachelor's degree in Electrical Engineering