Silicon Packaging Engineering Manager

Intel Corporation

IC Packaging Design Manager leading a team for advanced packaging solutions at Intel Foundry. Driving design execution for customer programs while overseeing engineers and project management.

Posted 6/16/2026full-timePhoenix • Arizona, California, Oregon • 🇺🇸 United StatesSeniorLead💰 $190,610 - $269,100 per yearWebsite

About the role

Key responsibilities & impact

Lead and manage a group of IC Packaging Engineers, providing guidance, mentorship, and support to ensure the successful execution of projects.
Oversee the planning, scheduling, and execution of package design projects, ensuring that milestones and deadlines are met.
Foster a collaborative and innovative team environment, encouraging continuous learning and professional development.
Lead design groups, coordinating efforts across multiple teams to achieve project goals.
Serve as the primary package design technical lead and guide customers through end-to-end package design flow.
Drive the development of advanced packaging designs, ensuring compliance with industry standards and best practices.
Collaborate with cross-functional teams, including package architects, silicon and board design teams, design rule owners, electrical analysis engineers, and integration teams to define and implement design specifications.
Ensure products are designed and developed with high quality standards by overseeing design processes, risk management, and compliance throughout the product design lifecycle, working closely with cross-functional teams to identify and address potential quality issues before they arise.
Develop and maintain detailed project plans, including resource allocation, risk management, and progress tracking.
Coordinate with stakeholders to ensure alignment on project goals, deliverables, and timelines.

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering or STEM related field with 9+ years of relevant experience OR
Master's degree in Electrical Engineering or STEM related field with 6+ years of relevant experience OR
PhD in Electrical Engineering or STEM related field with 4+ years of relevant experience
Experience in IC Package, chiplet/SOC design, or heterogenous integration, with at least 3 years in a leadership role.
Proven experience in a leadership or management role, with a track record of successfully leading engineering teams and delivering complex projects within established timelines.
Experience in performance/manufacturability/yield aware design methodologies
Experience with design flows and methodologies (physical design, analysis, verification).
Experience working with IC Packaging EDA tools from Siemens and/or Cadence.
Experience with packaging technologies and heterogenous integration.
Preferred Qualifications: Experience with IC Packaging designs for HPC/AI class of products

Benefits

Comp & perks

Competitive pay
Stock bonuses
Health insurance
Retirement plans
Vacation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

IC Package designchiplet designSOC designheterogeneous integrationperformance aware designmanufacturability aware designyield aware designphysical designdesign analysisdesign verification

Soft Skills

leadershipmentorshipcollaborationproject managementrisk managementcommunicationteam coordinationproblem-solvinginnovationcontinuous learning