Collateral Design and DFM Engineer

Intel Corporation

Collateral Design and DFM Lead Engineer at Intel focusing on DFM for advanced logic technologies. Collaborating with cross-functional teams to improve performance and yield in semiconductor manufacturing.

Posted 6/5/2026full-timeSanta Clara • Arizona, California, Oregon • 🇺🇸 United StatesSeniorLead💰 $190,650 - $269,150 per yearWebsite

Tech Stack

Tools & technologies

Node.js

About the role

Key responsibilities & impact

Lead cross functional teams across process integration/ device/ yield/ design/OPC/RET/DR and DTP/CAD teams to define and enhance Design for Manufacturability rules for enhanced yield /performance and faster ramp on advanced logic technologies
Enhance and feed silicon learning / sighting of yield issues for design teams to update layout /DTCO methodologies, flows to capture yield issues early in the design process
Work and refine yield tools/flows inside foundry and help in inline yield detection and optimization
Define/Refine DFM methodologies by understanding silicon process flows and predicting and developing rules for avoiding layout and design marginalities by working with cross functional teams

Requirements

What you’ll need

Master or Ph.D. degree in Electrical Engineering, Physics, or related field with 10+ years of experience in DTCO and/or DFM within semiconductor foundry or advanced technology development environment
Strong understanding of DTCO skills including understanding of SRAM, Standard cells, Process Integration, Yield, and Device.
Experience in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects
Experience in scribe line layout design and process monitoring structure development
Proven track record in foundry environment developing and implementing DFM solutions for varied customer requirements across multiple market segments
Coding/Scripting knowledge beneficial
Ability to switch between multiple projects and ability to prioritize
Required exposure to foundry ecosystem with understanding of customer design flows and manufacturing constraints across various application domains
Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs, Backside power delivery
Understanding of Physical Design flows for Yield Analysis, DRC, and verification flows
Proficiency in design rule development, validation, and waiver management processes

Benefits

Comp & perks

competitive pay
stock bonuses
benefit programs which include health, retirement, and vacation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

DTCODFMSRAMStandard cellsProcess IntegrationYieldDevicescribe line layout designPhysical Design flowsdesign rule development

Soft Skills

leadershipproject managementprioritizationcross functional collaboration

Certifications

Master's degree in Electrical EngineeringPh.D. in Electrical Engineeringrelated field