Senior Staff Mixed Signal IP Enablement, Debug Engineer

Intel Corporation

Senior Staff Engineer in Mixed Signal IP Enablement at Intel's Hard IP Development Group. Develop and validate high-performance mixed signal IPs for diverse client applications.

Posted 6/2/2026full-timeFolsom • California • 🇺🇸 United StatesSenior💰 $164,470 - $311,890 per yearWebsite

Tech Stack

Tools & technologies

iOSPython

About the role

Key responsibilities & impact

Customer-Focused IP Enablement
Provide Response for IP Questions to customers timely
Provide IP reviews, Lab Demos, and Training to customers as needed
Generate Industry standard IP documentations and collaterals as needed for external customers
Partner closely with SoC customers and IP design teams to deliver comprehensive pre-silicon to post-silicon IP Integration and Debug support
Develop and execute test plans and content using AI-driven tools and Python/System Verilog scripting
Conduct SoC board design reviews and provide technical recommendations
Perform signal integrity and power integrity simulations to optimize design performance
Silicon Validation & Debug Leadership
Serve as the IP team representative during SoC power-on activities for test chips and products
Provide hands-on IP enabling support throughout the silicon bring-up process
Lead identification, investigation, and resolution of IP-related silicon issues
Execute timely debugging and disposition of customer issues and sightings
Technical Problem Solving
Conduct both pre-silicon and post-silicon issue reproduction and analysis
Drive root cause analysis initiatives with comprehensive failure analysis
Collaborate across cross-functional teams to deliver robust solutions
Maintain customer obsession by ensuring rapid resolution of IP-related challenges

Requirements

What you’ll need

Bachelors and 7+ years of experience or Masters degree and 4+ years of experience in Computer Engineering, Electrical Engineering, or in a related field
Experience in IP Integration, pre-silicon verification, Electrical or Functional Post Silicon validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die)
2+ years of experience with the lab hardware and software
Experience using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs (Bit Error Ratio Testers)
Experience with at least one or more industry standard IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet, etc. Either PHY or Controller experience is good

Benefits

Comp & perks

health
retirement
vacation

ATS Keywords

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Hard Skills & Tools

PythonSystem VerilogIP Integrationpre-silicon verificationpost-silicon validationsignal integrity simulationspower integrity simulationsroot cause analysisfailure analysistest plans

Soft Skills

customer-focusedtechnical problem solvingcollaborationleadershipcommunicationorganizational skillscustomer obsessioninvestigationresolutiontimely response