Mixed Signal Logic Design Engineer

Intel Corporation

Mixed Signal Logic Design Engineer at Intel developing RTL coding and simulation for high-speed IPs. Collaborates on architecture and microarchitecture features while ensuring design integrity for integration.

Posted 5/28/2026full-timeFolsom • California • 🇺🇸 United StatesMid-LevelSenior💰 $122,440 - $232,190 per yearWebsite

About the role

Key responsibilities & impact

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high quality integration of the IP block.

Requirements

What you’ll need

Bachelors with 4+ years of experience or master's with 3+ years of experience or PhD with 1+ years of experience in Computer Science or Computer Engineering or Electrical Engineering or related technical discipline
2+ years of experience with proficiency in RTL design and coding using System Verilog and Verilog.
Expertise in mixed signal fundamentals, low-power design using UPF, and clock gating.
Deep understanding of digital and analog design principles, clock domain crossing, and power-performance tradeoffs.
Experience with hardware simulation tools and methodologies (VCS/Verdi).
Familiarity with IP environment and configuration management tools
Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low power design.

Benefits

Comp & perks

competitive pay
stock bonuses
health
retirement
vacation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills & Tools

RTL designSystem VerilogVerilogmixed signal designlow-power designUPFclock gatingdigital design principlesanalog design principleshardware simulation